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62911hkpc 5-6520/72308hkim no.a1254-1/13 http://onsemi.com semiconductor components industries, llc, 2013 june, 2013 STK672-340-E overview the STK672-340-E is a unipolar fixed-current chopper type 2-phase stepping motor driver hybrid ic. it features power mosfets in the output stage and a built-in phase signal dist ribution ic. the incorporation of a phase distribution ic allows the STK672-340-E to control the speed of the motor ba sed on the frequency of an external input clock signal. it supports two types of excitation for motor control: 2-phas e excitation and 1-2 phase exc itation. it also provides a function for switching the motor direction. the STK672-340-E features an enable pin, a function not provided in the stk672-120-e. when the enable pin is set low while the clock signal is being supplied, all mosfet devices are forced to the off state. when enable is set high again later, the ic resumes operation, continuing with the prior excitation timing. applications ? two-phase stepping motor drive in send/receive facsimile units. ? paper feed in copiers, industrial robots, and other ap plications that require 2-ph ase stepping motor drive. ordering number : ena1254a thick-film hybrid ic unipolar fixed-current chopp er (external-excited pwm) scheme and built-in phase signal distribution ic two-phase stepping motor driver (square wave drive) output current 2.2a
STK672-340-E no.a1254-2/13 features ? the motor speed can be controlled by the frequency of an external clock signal (the clock pin signal). ? the excitation type is switched according to the state (low or high) of the mode pin. the mode is set to 2-phase or 1-2 phase excitation on the rising edge of the clock signal. ? a motor direction switching pin (the cwb pin) is provided. ? supports schmitt input for 2.5v high level input. ? the motor current can be set by changing the vref pin voltage. since a 0.14 current detection resistor is built in, a current of 1a is set for each 0.14v of applied voltage. ? the input frequency range for the clock signal used for motor speed co ntrol is 0 to 50khz. ? supply voltage ranges: v cc = 10 to 42v, v dd = 5.0v 5% ? this ic supports motor operating currents of up to 2.2a at tc = 105 c, and of up to 3.6a at tc = 25 c. ? provides a function that, during clock input, forces all mosfet devices to the off state when the enable pin is set low, and then, when enable is set high, resumes operation continuing with the prior excitation timing. specifications absolute maximum ratings at tc = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc max no signal 52 v maximum supply voltage 2 v dd max no signal -0.3 to +7.0 v input voltage v in max logic input pins -0.3 to +7.0 v output current i oh max v dd = 5v, clock 200hz 3.6 a allowable power dissipation pd max with an arbitrarily large heat sink. per mosfet 8 w operating substrate temperature tc max 105 c junction temperature tj max 150 c storage temperature tstg -40 to +125 c allowable operating ranges at ta = 25 c parameter symbol conditions ratings unit operating supply voltage 1 v cc with signals applied 10 to 42 v operating supply voltage 2 v dd with signals applied 5.0 5% v input voltage v ih 0 to v dd v output current 1 i oh 1 tc=105 c, clock 200hz 2.2 a output current 2 i oh 2 tc=80 c, clock 200hz, see the motor current (i oh ) derating curve 2.7 a clock frequency f cl minimum pulse width: at least 10 s 0 to 50 khz phase driver withstand voltage v dss i d =1ma (tc=25 c) 100min v recommended operating substrate temperature tc no condensation 0 to 105 c electrical characteristics at tc = 25 c, v cc = 24v, v dd = 5v rating parameter symbol conditions min typ max unit v dd supply current i cco clock=gnd 3.1 7 ma output average current ioave with r/l=3 /3.8mh in each phase vref = 0.137v 0.52 0.58 0.64 a fet diode forward voltage vdf if=1a (r l =23 ) 1.1 1.7 v output saturation voltage vsat r l =23 0.31 0.44 v input high voltage v ih pins 8 to 12 (5 pins) 2.5 v input low voltage v il pins 8 to 12 (5 pins) 0.6 v input current i il with pins 8 to 12 at the ground level. 10 a vref input voltage vrh pin 7 0 3.5 v vref input bias current i ib with pin 7 at 1v 50 500 na pwm frequency fc 35 45 55 khz note: a fixed-voltage power supply must be used. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
STK672-340-E no.a1254-3/13 package dimensions unit:mm (typ) internal equivalent circuit block diagram 1 12 46.6 41.2 12.7 25.5 (9.6) 11 2=22 3.6 0.5 2.0 8.5 4.0 0.4 2.9 1.0 8 6 5 a 10 11 9 4 ab 3 b 2 bb 1 gnd v dd (5v) v dd v ss mode clock cwb resetb 12 7 resetb mode clock cwb resetb resetb vref f1 fao fab fbo fbb ai bi ci f2 f3 f4 r1 r2 itf02169 excitation mode selection phase advance counter phase excitation signal generation chopping circuit
STK672-340-E no.a1254-4/13 sample application circuit ? to minimize noise in the 5v system, lo cate the ground side of ca pacitor co2 in the above circuit as close as possible to pin 1 of the ic. also, if at all possible, the ground used for vref must not be common to the p.gnd pattern, but must be directly wired from pin 1. ? insert resistor ro3 (47 to 100 ) so that the discharge energy from capacito r co4 is not directly applied to the cmos ic in this hybrid device. if the diode d1 has vf characteristics with vf less than or equal to 0.6v (when if = 0.1a), this will be smaller than the cmos ic input pin diode vf . if this is the case ro3 may be replaced with a short without problem. ? apply 2.5v high level input to pins 8, 9, 10, 11, and 12. ? since the input pins do not have built-in pull-up resistors, when the open-collector type pins 8, 9, 10, 11, and 12 are used as inputs, a 10 to 47k pull-up resistor (to v dd ) must be used. ? to prevent incorrect opera tion due to chopping noise, we recommend inserting 470 to 1000pf capacitors between pin 1 and each of the pins 8, 9, 10, and 12. (with the open-collector type ic, we also recommend in serting a 470 to 1000pf capacitor between pin 11 (resetb) and pin 1 when pin 11 is used as an input.) ? the following circuit (for a lowered current of over 0.2a ) is recommended if the application needs to temporarily lower the motor current. here , a value of close to 100k must be used for resistor ro1 to make the transistor output saturation voltage as low as possible. 5v ro1 ro2 ro3 vref 5v ro1 ro2 ro3 vref itf02172 itf02171 v dd =5v clock mode cwb 5v 5v resetb 6 9 8 10 11 7 enable 12 d1 ro3 ro4 20k co4 10 f ro1 vref ro2 0.1 f co1 co3 + + + 10 f 5 a 4 ab 3 b 2 bb 1 gnd STK672-340-E co2 at least 100 f v cc 24v p.gnd itf02170 2-phase stepping motor
STK672-340-E no.a1254-5/13 ? motor current peak value i oh setting i oh = vref rs vref = (ro2 (ro1 + ro2)) 5v (or 3.3v) rs is the hybrid ic internal current detection resistor. in the stk672-330-e (and stk672-350-e) rs is 0.195 . (in the STK672-340-E and stk672-360-e, rs is 0.14 .) input pin functions pin name pin no. function input conditions when operating clock 9 reference clock for motor phase current sw itching operates on the rising edge of the signal mode 8 excitation mode selection low: 2-phase excitation high: 1-2 phase excitation cwb 10 motor direction switching low: cw (forward) high: ccw (reverse) resetb 11 system reset and a, ab , b, and bb outputs cutoff. applications must apply a reset signal for at least 10 s when v dd is first applied. a reset is applied by a low level enable 12 the a, ab, b, and bb outputs are turned off, and after operation is restored by returning the enable pin to the high level, operation continues with the same excitation timing as before the low-level input. the a, ab, b, and bb outputs are turned off by a low- level input. (1) a simple reset function is formed from d1, co4, ro3, and ro4 in this application circuit. with the clock input held low, when the 5v supply voltage is brought up a reset is applied if the motor output phases a and bb are driven. if the 5v supply voltage rise time is slow (over 50ms), the motor output phases a and bb may not be driven. increase the value of the capacitor co 4 and check circuit operation again. (2) see the timing chart for the concrete details on circuit operation. usage notes 1. STK672-340-E input signal functions and timing (specifications common to the stk672-330-e as well) (all inputs have no internal pull-up resistor.) [resetb and clock (input signal timi ng when power is first applied)] as shown in the timing chart, a resetb signal input is requ ired by the driver to operate with the timing in which the f1 gate is turned on first. the resetb signal timing must be set up to have a width of at least 10 s, as shown below. the capacitor co4, and the resistors ro3 and ro4 in the app lication circuit form simple reset circuit that uses the rc time constant rising time. however, when designing the resetb input based on v ih levels, the application must have the timing shown in figure 1. figure 1 resetb and clock signals input timing i oh 0 itf02173 at least 10 s at least 5 s rise of the 5v supply voltage resetb signal input clock signal itf02174
STK672-340-E no.a1254-6/13 [clock (phase switching clock)] ? input frequency: dc to 50khz ? minimum pulse width: 10 s ? signals are read on the rising edge. [cwb (motor direction setting)] the direction of rotation is switched by setting cwb to 1 (hig h) or 0 (low). see the timing charts for details on the operation of the outputs. note: the state of the cwb input must not be changed during the 6.25 s period before and after the rising edge of the clock input. [enable (forcible on/off control of the a, ab, b, and bb outputs, and selection of the operate or hold state for hybrid ic internal operation)] enable = 1 (high): normal operation enable = 0 (low): outputs a, ab, b, and bb forced to the off state. if, during the state where clock signal input is provided , the enable pin is set to 0 (low) and then is later restored to the 1 (high) state, the ic will resume operatio n with the excitation timing continued from before the point enable was set to 0 (low). [mode (excitation mode selection)] mode = 0 (low): 2-phase excitation mode = 1 (high): 1-2 phase excitation see the timing charts for details on output operation in these modes. note: the state of the mode input must not be changed during the 5 s period before and after the rising edge of the clock input. 2. allowable motor current operating range the motor current (i oh ) must be held within the range corresponding to the area under the curve shown in figure 3. for example, if the operating substrat e temperature tc is 105c, then i oh must be held under i oh = 2.2a, and in hold mode i oh must be held under i oh = 1.8a. 3. thermal design [operating range in which a heat sink is not used] this section discusses the safe operatin g range when no heat sink is used. in the maximum ratings specifications, tc max is specified to be 105c, and when mounted in an actual end product system, the tc max value must never be exceeded during operation. tc can be expressed by formula (a) below, and thus the range for tc must be stipulated so that tc is always under 105c. tc = ta + tc (a) ta: hybrid ic (hic) ambient temperature, tc: temperature increase across the aluminum substrate as shown in figure 5, the value of tc increases as the hybrid ic internal average power dissipation p d increases. as shown in figure 4, p d increases with the motor current. here we describe the actual p d calculation using the example shown in the motor curr ent timing chart in figure 2. since there are periods when current flows and periods when the current is off during actual motor operation, p d cannot be determined from the data presente d in figure 4. therefore, we calculate p d assuming that actual motor operation consists of repetitions of the operation shown in figure 2. figure 2 motor current timing t1 t2 t0 t3 -i o 1 i o 2 i o 1 motor phase current (sink side) itf02175
STK672-340-E no.a1254-7/13 t1: motor rotation operation time t2: motor hold operation time t3: motor current off time t2 may be reduced, depending on the application. t0: single repeated motor operating cycle i o 1 and i o 2: motor current peak values due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. note that figure 2 presents the concepts here, and that the on/off duty of the actual signals will differ. the hybrid ic (hic) internal average power dissipation p d can be calculated from the following formula. p d = (t1 p1 + t2 p2 + t3 0) t0 (i) (here, p1 is the p d for i o 1 and p2 is the p d for i o 2) if the value calculated in formula (i) abov e is under 1.5w, then from figure 5 we see that operation is allowed up to an ambient temperature ta of 60c. while the operating range when a heat sink is not used can be determined from formula (i) above, figure 4 is merely a single example of one opera ting mode for a single motor. for example, while figure 4 shows a 2- phase excitation motor, if 1-2 phase excitation is used with a 500hz clock frequency, the drive will be turned off for 25% of the time and the dissipation p d will be reduced to 75% of that in figure 4. it is extremely difficult for calculate the internal average power dissipation p d for all possible end product conditions. after performing the above rough calculations, always install the hybrid ic (hic) in an actual end product and verify that the substrate temperature tc does not rise above 105c. [operating range in which a heat sink is used] although a heat sink is attached to lower tc if the hybrid ic (hic) internal average power dissipation p d increases, the resulting size can be found using the value of c-a in equation (ii) below and the graph depicted in figure 6. c-a= (tc max-ta) p d ---------------------------- (ii) tc max: maximum operating substrate temperature =105 c ta: hic ambient temperature although a heat sink can be designed based on equations (i) and (ii) above, be sure to mount the hic in a set and confirm that the substrate temperature, tc, is 105 c or less. the average hic power loss, p d , described above represents the power lo ss when there is no avalanche operation. to add the loss during avalanche operations, be sure to add equation (2), ?allowa ble stk672-3** avalanche energy value?, to p d . 10 23 57 100 1000 23 57 1.0 2 3 5 7 10 100 2 3 5 7 itf02652 figure 6 c-a - s heat sink area, s - cm 2 heat sink thermal resistance, c-a - c/w w i t h n o s u r f a c e f i n i s h w ith a f la t b la c k s u r f a c e f in is h
STK672-340-E no.a1254-8/13 4. STK672-340-E allowabl e avalanche energy value [allowable range in avalanche mode] when driving a 2-phase stepping motor with constant current chopping using an stk672-3** series hybrid ic, the waveforms shown in figure 7 below result for the output current, i d , and voltage, v ds . figure 7 output current, i d , and voltage, v ds , waveforms 1 of the stk672-3** series when driving a 2-phase stepping motor with constant current chopping when operations of the mosfet built into stk672-3** seri es ics is turned off for constant current chopping, the i d signal falls like the waveform shown in the figure above. at this time, the output voltage, v ds , suddenly rises due to electromagnetic induction generated by the motor coil. in the case of voltage that rises suddenly , voltage is restricted by the mosfet v dss . voltage restriction by v dss results in a mosfet avalanche. during avalanche operations, i d flows and the instantaneous energy at this time, eavl1, is represented by equation (1). eavl1=v dss iavl 0.5 tavl ------------------------------------------- (1) v dss : v units, iavl: a units, tavl: sec units the coefficient 0.5 in equation (1) is a constant required to convert the iavl triangle wave to a square wave. during stk672-3** series operations, the waveforms in the figure above repeat due to the constant current chopping operation. the allowable avalanche energy, eavl, is therefore represented by equation (2) used to find the average power loss, pavl, during avalanche mode multiplied by the chopping frequency in equation (1). pavl=v dss iavl 0.5 tavl fc ------------------------------------------- (2) fc: hz units (fc is set to the pwm frequency of 50khz.) for v dss , iavl, and tavl, be sure to actually operate th e stk672-3** series and substitute values when operations are observed using an oscilloscope. ex. if v dss =110v, iavl=1a, tavl=0.2 s when using a STK672-340-E driver, the result is: pavl=110 1 0.5 0.2 10 -6 50 10 3 =0.55w v dss =110v is a value actually measured using an oscilloscope. the allowable loss range for the allowable avalanche ener gy value, pavl, is shown in the graph in figure 9. when examining the avalanche energy, be sure to actually drive a motor and observe the i d , v dss , and tavl waveforms during operation, and then check that the result of calculating equation (2) falls within the allowable range for avalanche operations. v dss : voltage during avalanche operations i oh : motor current peak value iavl: current during avalanche operations tavl: time of avalanche operations v ds i d itf02557
STK672-340-E no.a1254-9/13 [i d and v dss operating waveforms in non-avalanche mode] although the waveforms during avalanche mode are given in figure 7, sometimes an avalanche does not result during actual operations. factors causing avalanche are listed below. ? poor coupling of the motor?s phase coils (electromagnetic coupling of a phase and ab phase, b phase and bb phase). ? increase in the lead inductance of the harness caused by the circuit pattern of the p.c. board and motor. ? increases in v dss , tavl, and iavl in figure 7 due to an increase in the supply voltage from 24v to 36v. if the factors above are negligible, the waveforms shown in figure 7 become waveforms without avalanche as shown in figure 8. under operations shown in figure 8, avalanche does not occur and there is no need to consider the allowable loss range of pavl shown in figure 9. figure 8 output current, i d , and voltage, v ds , waveforms 2 of the stk672-3** series when driving a 2-phase stepping motor with constant current chopping figure 9 allowable loss range, pavl-i oh during STK672-340-E avalanche operations note: the operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. because it is possible to apply 3.0w or more at i oh =0a, be sure to avoid using the mosfet body diode that is used to drive the motor as a zener diode. [smoke emission precuations] if any of the output pins 2, 3, 4, and 5 is held open, the electrical stress onto the driver due to the inductive energy accumulated in the motor could cause short-circuit follo wed by permanent damage to the internal mosfet. as a result, the STK672-340-E may give rise to emit smoke. v ds i d itf02558 i oh : motor current peak value 0 0.5 1.0 1.5 3.5 3.0 2.5 2.0 0.5 0 itf02653 4.5 4.0 5.0 3.5 2.5 3.0 2.0 1.5 1.0 t c = 8 0 c 1 0 5 c pavl - i oh motor phase current, i oh - a average power loss in the avalanche state, pavl - w
STK672-340-E no.a1254-10/13 timing charts 2-phase excitation 1-2 phase excitation mode reset cwb clock enable fao fab fbo fbb mode reset cwb clock enable fao fab fbo fbb
STK672-340-E no.a1254-11/13 1-2 phase excitation (cwb) switching from 2-phase to 1-2 phase excitation mode reset cwb clock enable fao fab fbo fbb mode reset cwb clock enable fao fab fbo fbb
STK672-340-E no.a1254-12/13 1-2 phase excitation (enable) mode reset cwb clock enable fao fab fbo fbb 10 20 0 30 40 50 110 60 70 80 90 100 0 1.0 0.5 4.0 3.0 3.5 2.0 2.5 1.5 itf02650 0.5 0 1.0 4.0 3.0 3.5 1.5 2.0 2.5 0 6 2 4 16 14 10 12 8 itf02651 motor current, i oh - a substrate temperature, tc - c i oh - tc internal average power dissipation, p d - w motor current, i oh - a p d - i oh substrate temperature rise, tc - c hybrid ic internal average power dissipation, p d - w tc - p d 0.5 0 1.0 1.5 3.5 2.0 2.5 3.0 0 40 10 20 30 80 60 70 50 itf02178 v cc =24v, v dd =5.0v 500hz, 2 phase excitation motor r=0.63 l=0.62mh 200hz 2 phase excitation hold mode figure 5 figure 3 figure 4
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